1. Field of the Invention
The present invention relates to a level converting circuit and, more particularly, to a circuit for converting a level of a low-amplitude input which, built in a thin-film transistor integrated circuit or the like, functions as its clock interface and pulse-amplifies a low-amplitude input clock signal.
2. Description of the Related Art
FIG. 7 shows an example of a conventional level converting circuit. This level converting circuit 101 is built in a thin-film transistor (TFT) integrated circuit 102 to function as its clock interface. The level converting circuit 101 comprises a current mirror circuit containing a pair of input transistors mn1 and mn2 and a pair of load transistors mp1 and mp2. Each of the input transistors is the thin-film transistor of n-channel field-effect transistor (FET) type. Each of the load transistors is the thin-film transistor of p-channel FET type. Gates of the pair of input transistors mn1 and mn2 are supplied with a clock signal CK1 and a clock signal CK2 respectively. These clock signals are opposite to each other in phase. The current mirror circuit is applied with a supply voltage VDD to output a pulse-amplified output clock signal Vout in response to the input clock signals CK1 and CK2. The output clock signal Vout is used as an internal clock of the thin-film transistor integrated circuit 102. The thin-film transistor integrated circuit 102 has a relatively high operating voltage, the supply voltage VDD being about 11 V to 14 V for example. The pair of input clock signals CK1 and CK2 are supplied from a timing generator (TG) 103. The timing generator 103 is generally composed of a CMOS gate array formed on a silicon chip, its supply voltage being relatively low.
Referring to FIG. 8, a problem to be solved by the invention will be briefly described. As shown in FIG. 8(a) the conventional level converting circuit 101 pulse-amplifies the output clock signal Vout in response to the input clock signal CK1. At this time, an amplitude (a peak potential) of the input clock signal CK1 needs to be somewhat higher than a threshold value Vth of the input transistor mn1. For example, if the threshold value Vth is 3 V, the peak potential of the input clock signal needs to be 4 V or higher. As shown in FIG. 8(b) if the peak potential of the input clock signal CK1 is lower than the threshold value Vth, the input transistor mn1 does not conduct sufficiently, providing no proper output clock signal Vout.
The external timing generator 103, which supplies the input clock signal, is made up of a CMOS gate array in general. Recently, a supply voltage necessary for driving the gate array has been lowering quickly from conventional 5 V to 3.3 V or lower. A clock signal supplied by such a low-voltage timing generator as mentioned above is sometimes lower than the TFT threshold value on the thin-film transistor integrated circuit. This problem makes it very difficult for directly interfacing between the low-voltage CMOS gate array and the thin-film transistor integrated circuit.
In a conventional example shown in FIG. 7, the level converting circuit is operated by using two-phase input clocks CK1 and CK2 opposite to each other in polarity. This consequently requires a pair of connecting terminals as clock interface. As the number of necessary internal clocks increases, the number of clock interface connecting terminals increases, complicating a wiring job and preventing compact device packaging. To solve these problems, a level converting circuit which operates on a single-phase input clock signal has been proposed. FIG. 9 shows an example of such a circuit. Basically, this circuit has generally the same constitution as that of the two-phase input level converting circuit shown in FIG. 7. In the figure, common parts are assigned with common reference numerals for ease of understanding. The single-phase input level converting circuit is different from the single-phase counterpart in that a gate of the input transistor mn2 is applied with a fixed DC bias VG instead of the inverted input clock signal CK2.
Referring to FIG. 10, an operation of the single-phase input level converting circuit of FIG. 9 will be described briefly. When the input clock signal CK goes high, the input transistor mn1 and the load transistor mp2 conduct, upon which the pulse-amplified output clock signal Vout rises. Then, when the input clock signal CK goes low, the load transistor mp2 stops conducting and, at the same time, the input transistor mn2 applied with the fixed bias VG operates, causing the output clock signal Vout to fall. To perform this operation stably, it is necessary to properly set the fixed bias VG based on the peak potential of the input clock signal CK and the threshold voltage of the input transistor mn2. Actually, however, it is extremely difficult to set the fixed bias VG in an internal circuit approach. Also, even if the fixed bias VG is externally applied, very fine adjustment is required, thereby hampering practicality. Like the two-phase input level converting circuit of FIG. 7, the single-phase input level converting circuit of FIG. 9 cannot provide the proper output clock signal Vout if the peak potential of the input clock signal goes below the threshold voltage of the input transistor.